/**
 * @file    gt9881_misc.h
 * @author  Giantec-Semi ATE
 * @brief   CMSIS GT98xx Device Peripheral Access Layer Header File
 * @version 0.1
 * 
 * @copyright Copyright (c) 2021 Giantec-Semi
 * 
 */

#pragma once
/** Define to prevent recursive inclusion */
#ifndef __GT9881_MISC_H__
#define __GT9881_MISC_H__

#ifdef __cplusplus
    extern "C" {
#endif /* __cplusplus */

#include "gt9881.h"
typedef struct tagMISCTypedef {
  __IO uint32_t DAC_HALL_OS_REG;
  __IO uint32_t OCP_REG;
  __IO uint32_t DAC_HALL_IB_REG;
  __IO uint32_t SMA_REG;
  __IO uint32_t TMR_DAC_VB_REG;
  __IO uint32_t TMR_DAC_OS1_REG;
  __IO uint32_t TMR_DAC_OS2_REG;
  __IO uint32_t OSC_REG;
  __IO uint32_t DAC12_EN_REG;
  __IO uint32_t IREF_REG;
  __IO uint32_t IREF_8U_REG;
  __IO uint32_t IREF_PWM_REG;
  __IO uint32_t LDO_REG;
  __IO uint32_t VM_DET_EN_REG;
  __IO uint32_t DAC_VM_DET_REG;
  __IO uint32_t TEST_MODE_REG;
  __IO uint32_t DRV_OS_TRIM_REG;
  uint32_t RESERVED0[3];                        ///< Reserved
  __IO uint32_t IO_VDD_INT_CLR_REG;
  __IO uint32_t VM2_INT_CLR_REG;
  __IO uint32_t VM1_INT_CLR_REG;
  __IO uint32_t TSD_INT_CLR_REG;
  __IO uint32_t UVLO_INT_CLR_REG;
  
} MISCTypedef;
/** @} Peripheral_Registers_Structures */

/**
 * @addtogroup Peripheral_Memory_Map
 * @{
 */
#define MISC_BASE                   (PERIPH_BASE + 0x16000UL)    ///< MISC base address

/** @} Peripheral_Memory_Map */

/**
 * @addtogroup Peripheral_Declaration
 * @{
 */
#define MISC                        ((MISCTypedef*)MISC_BASE)   ///< ADC operator
/** @} Peripheral_Declaration */


#define MISC_DAC_HALL_0S_REG            (*(__IO uint32_t *)(MISC_BASE+0x00000000))
#define MISC_OCP_REG                    (*(__IO uint32_t *)(MISC_BASE+0x00000004))
#define MISC_HALL_IB_REG                (*(__IO uint32_t *)(MISC_BASE+0x00000008))
#define MISC_SMA_REG                    (*(__IO uint32_t *)(MISC_BASE+0x0000000C))
#define MISC_TMR_DAC_VB_REG             (*(__IO uint32_t *)(MISC_BASE+0x00000010))
#define MISC_TMR_DAC_0S1_REG            (*(__IO uint32_t *)(MISC_BASE+0x00000014))
#define MISC_TMR_DAC_OS2_REG            (*(__IO uint32_t *)(MISC_BASE+0x00000018))
#define MISC_OSC_REG                    (*(__IO uint32_t *)(MISC_BASE+0x0000001C))
#define MISC_DAC12_EN_REG               (*(__IO uint32_t *)(MISC_BASE+0x00000020))
#define MISC_IREF_REG                   (*(__IO uint32_t *)(MISC_BASE+0x00000024))
#define MISC_IREF_8U_REG                (*(__IO uint32_t *)(MISC_BASE+0x00000028))
#define MISC_IREF_PWM_REG               (*(__IO uint32_t *)(MISC_BASE+0x0000002C))
#define MISC_LDO_REG                    (*(__IO uint32_t *)(MISC_BASE+0x00000030))
#define MISC_VM_DET_EN_REG              (*(__IO uint32_t *)(MISC_BASE+0x00000034))
#define MISC_DAC_VM_DET_REG             (*(__IO uint32_t *)(MISC_BASE+0x00000038))
#define MISC_TEST_MODE_REG              (*(__IO uint32_t *)(MISC_BASE+0x0000003C))
#define MISC_DRV_OS_TRIM_REG            (*(__IO uint32_t *)(MISC_BASE+0x00000040))
#define MISC_IO_VDD_INT_CLR_REG         (*(__IO uint32_t *)(MISC_BASE+0x00000050))
#define MISC_VM2_INT_CLR_REG            (*(__IO uint32_t *)(MISC_BASE+0x00000054))
#define MISC_VM1_INT_CLR_REG            (*(__IO uint32_t *)(MISC_BASE+0x00000058))
#define MISC_TSD_INT_CLR_REG            (*(__IO uint32_t *)(MISC_BASE+0x0000005C))
#define MISC_UVLO_INT_CLR_REG           (*(__IO uint32_t *)(MISC_BASE+0x00000060))


#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* __GT9881_IWDT_H__ */


